The asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is a mixed signal design with an external sampling clock and an internally generated asynchronous clock for producing successive digital N-bit outputs. In order for all N-bits to be properly received, it is necessary that the cycle of the external clock is sufficiently long to allow all N bits to be received based on the internal asynchronous clock.
The clock cycle of the external sampling clock is generally constant and known. However, the internal asynchronous clock has a variable cycle that can vary from bit to bit and from sample to sample. The average cycle length may also vary with temperature and process corner. Thus, normally the external clock speed is set sufficiently slow to ensure that even in the worst case scenario all N bits, which are dependent on the speed of the internal clock, would be received. There are currently no ways to measure or automatically regulate the cycle time of the internal asynchronous clock.